IEEE Windsor Section


Archive for the ‘Uncategorized’ Category

Past Event

Wednesday, August 26th, 2015

Young professional chapter of IEEE Windsor is holding its first event on August 27, 2015.

The details of the event are presented in the following link:

Past Event

Wednesday, August 26th, 2015

The opportunity to Nominate yourself for Appointment to fill a 2015 opening in a Chapter officer position is now available. In addition, this opportunity is now open and will remain open until the middle of September 2015.

For the Chapter II, Communications & Signal Processing Societies, the following are the Officer positions which are currently vacant and available for appointment:

  • Vice-Chair (Communications Society)
  • Vice-Chair (Signal Processing Society)
  • Secretary
  • Treasurer

Detail officer job descriptions are available through the IEEE Center for Leadership Excellence at:

  • Note: Candidates for an officer position must be active (paid up) members (Graduate Student or higher grade) of IEEE as well as members of the society for which they are seeking election.

Submit your nominations for Appointment of 2015 Chapter II Officers at:

Please contact Chair of chapter, Dr. Tepe ( or ( if you have any question.

Past Event

Thursday, July 23rd, 2015

The following free presentation is held by IEEE Women in Engineering  and is available to all students and faculty members:

Presentation: Technical discussion on “Hardware and Software prototyping platforms

Date: July 30, 2015    5:30 pm- 7:00pm

Venue: 1102 CEI

Please refer to the following link for more detail:

Presentation_wie (1)

Past Event

Thursday, July 23rd, 2015

Title: Research Ethics and Presentation Skills

Presenter: Dr. Majid Ahmadi

Location: RCIM Lab

Date: Friday July 24, 2015 at 10:00am

RCIM members are welcome to attend


Past Event

Thursday, July 16th, 2015

Title: Energy harvesting systems: overview, technologies and applications

Friday , July 24, 2015, 3:00 – 3:45 PM

University of Windsor; Center for Engineering innovation, Room # 3000

Please refer to the following link for more detail,


Past Event

Wednesday, May 13th, 2015

Evaluation of Xilinx Vivado high-level-synthesis to design a TCP/IP protocol engine

Co-sponsored by RCIM Lab.

Presenter: Andreas Kugel of Academic staff member of Heidelberg University at Mannheim, ZITI (Institute of Computer Engineering)

Date: 15-May-2015
Time: 10:00AM to 11:00AM (1.00 hours)

High-level-synthesis (HLS) tools are essential to enable profiting from FPGA-technology in mainstream computing applications.  To date, problems  with regular patterns of data access and computation can be handled, at least to a certain  extent,  using  state-of-the-art  tools like OpenCL, Vivado HLS and others. Reliable, high bandwidth, low latency data transmission is a common issue in many Physics experiment and many actual solutions involve FPGA technology.

However, the requirement on reliability is frequently sacrificed in favor of bandwidth and low latency, due to the complexity of the issue. and custom or simple standard networking protocols like UDP are employed. This work tries to assess the applicability of Vivado HLS to implement the reliable TCP/IP networking protocol starting from a software model in “C”. Major topics to be addressed are implementation of the TCP state machine and buffer management. Results of a TCP data transmitter prototype implementation on a Xilinx Zynq evaluation board shall be presented.

Please check the following link for more detail:

Please check the following link for registration: