Past Event
Evaluation of Xilinx Vivado high-level-synthesis to design a TCP/IP protocol engine
Co-sponsored by RCIM Lab.
Presenter: Andreas Kugel of Academic staff member of Heidelberg University at Mannheim, ZITI (Institute of Computer Engineering)
Date: 15-May-2015
Time: 10:00AM to 11:00AM (1.00 hours)
High-level-synthesis (HLS) tools are essential to enable profiting from FPGA-technology in mainstream computing applications. To date, problems with regular patterns of data access and computation can be handled, at least to a certain extent, using state-of-the-art tools like OpenCL, Vivado HLS and others. Reliable, high bandwidth, low latency data transmission is a common issue in many Physics experiment and many actual solutions involve FPGA technology.
However, the requirement on reliability is frequently sacrificed in favor of bandwidth and low latency, due to the complexity of the issue. and custom or simple standard networking protocols like UDP are employed. This work tries to assess the applicability of Vivado HLS to implement the reliable TCP/IP networking protocol starting from a software model in “C”. Major topics to be addressed are implementation of the TCP state machine and buffer management. Results of a TCP data transmitter prototype implementation on a Xilinx Zynq evaluation board shall be presented.
Please check the following link for more detail:
http://site.ieee.org/sb-uwindsor/files/2015/05/IEEE_Section_Windsor_May_15th.pdf
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